النشر المحلي والعالمي:
| Alkurwy, Salah. (2021). Design and Implementation of Parallel Multiplier Using Two Split Circuits. PRZEGLĄD ELEKTROTECHNICZNY. 1. 21-24. 10.15199/48.2021.07.04. |
| Salah Hasan Ibrahim, Sawal Hamid Md Ali, Md. Shabiul Islam, “12-Bit High Speed Direct Digital Frequency Synthesizer Based On Pipelining Phase Accumulator Design”, Journal of Asian Scientific Research 2(11),PP.667-672, 2012. |
| Salah Hasan Ibrahim, Sawal Hamid Md Ali, Md. Shabiul Islam, “High Speed Direct Digital Frequency Synthesizer Using a New Phase accumulator”, Australian Journal of Basic and Applied Sciences PP.393-397, (11) 5, 2011. |
| Salah Hasan Ibrahim, Sawal Hamid Md Ali, Md. Shabiul Islam, “Design A 24-Bits Pipeline Phase Accumulator For Direct Digital Frequency Synthesizer phase”, International Synopsion on Instrumtention & Measurement, Sensor Network and Automation ( IMSNA) 2012 DOI: 10.1109/MSNA.2012.6324603; Publisher: IEEE |
| Salah Hasan Ibrahim, Sawal Hamid Md Ali, Md. Shabiul Islam, “High Speed Direct Digital Frequency Synthesizer with Pipelining Phase Accumulator Based on Brent-Kung Adder”,ICSE2012 Proc. 2012, Kuala Lumpur, Malaysia DOI: 10.1109/SMElec.2012.6417205; Publisher: IEEE |
| Salah Hasan Ibrahim, Sawal Hamid Md Ali, Md. Shabiul Islam, “Implementation of 32-bit High Speed Phase Accumulator For Direct Digital Frequency Synthesizer”, Asian Journal of Scientific Research, 2014, DOI: 10.3923/ajsr.PP.118.124, 2014. |
| Salah Hasan Alkurwy, Sawal Hamid Md Ali, Md. Shabiul Islam, “Implementation of Low Power Compressed ROM for Direct Digital Frequency Synthesizer”, IEEE-ICSE2014 Proc. 2014, Kuala Lumpur, Malaysia DOI: 10.1109/SMELEC.2014.6920859; Publisher: IEEE. |
| Salah Hasan Ibrahim, Sawal Hamid Md Ali, Md. Shabiul Islam, “Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer”, Scientific World Journal 2014 10.1155/2014/131568. |
| Salah Alkurwy, Sawal Hamid Md Ali, Md. Shabiul Islam, “A Novel ROM Design for High Speed DDFS” / Book / LAMBERT 2014, ISSN: 978-3-659-56639-4. |
| Design of A High-Performance Multiplier Based on Multiplex “International Journal of Engineering & Technology”, ISSN: 2227-524X Issue: 4, Vol : 7, Dec. 2018 |
| A Novel Approach of Multiplier Design Based on BCD Decoder, “Indonesian Journal of Electrical Engineering and Computer Science” ISSN: 2502-4752 Issue: 1, Vol : 14, April, 2019, |
| FPGA Implementation of FIR Filter Design Based on Novel Vedic Multiplier,“International Review on Modelling and Simulations”, ISSN: 1974-9821 Issue: 2, Vol: 12, April 2019, |
|
