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Yasir Amer Abbas Al-Zubaidi was awarded the Bachelor of Science (First Class Hons.) Degree and Master of Science Degree in Computer Engineering from the University of Technology, Iraq, in the year 2000 and 2005, respectively. His PhD in Computer Engineering from the Universiti Tenaga National, Malaysia at 2016. He has been part of the Centre of Automation and Embedded Computing Systems (CAECS) research team. Currently he is a Lecture in the Computer Engineering Department, College of Engineering, University of Diyala, Iraq. His research interests are in the fields of computer engineering including, Computer Architectures, embedded systems hardware-software co-design and Lightweight cryptography. He has authored and co-authored numerous publications in international journals and conferences. He is a member of the IEEE and the IEEE Computer Society since 2012. He has also received several awards and recognitions throughout his PhD studies such as best paper award (PECON 2014), Silver medal in Korea, Seoul International Invention Fair 2014 (SIIF14) |
Time Table
Lectures
Computer ArchitectureI
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Topics |
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Seconds Semester |
Fundamentals of Quantitative Design and Analysi |
Seconds Semester |
Memory Hierarchy Design
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Seconds Semester |
Instruction-Level Parallelism and Its Exploitation
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Seconds Semester |
Data-Level Parallelism in Vector, SIMD, and GPU Architectures |
Seconds Semester |
Multiprocessors and Thread-Level Parallelism
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Reference |
Computer Architecture A Quantitative Approach, Fifth Edition
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DSD
Topics |
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First Semester |
Introduction in the digital circuits |
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First Semester |
Design of combinational Logic circuits |
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First Semester |
Modeling combinational logic |
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First Semester |
Modeling sequential logic |
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First Semester |
Complementary metal Oxide Semiconductor |
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First Semester |
Programmable Logic Array |
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First Semester |
Programmable Array Logic |
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First Semester |
Programmable Logic Devices |
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Second Semester |
Design of combinational Circuits using |
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Second Semester |
Design of memory circuits |
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Second Semester |
To design and implement synchronous sequential circuits |
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Second Semester |
How logic is controlled |
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Second Semester |
Mealy/Moore state machines |
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Second Semester |
State diagrams & state tables |
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1. Charles H.Roth, Jr. “Fundamentals of Logic Design”, 4th Edition. Publishing House, Cengage Earning, 5th ed, 2005 2. Donald D.Givone, “Digital Principles and Design”, Tata McGraw-Hill, 2007 |
Important link
class 0nline
https://classroom.google.com/u/0/c/NTg3NTk0OTkzOFpa
https://classroom.google.com/u/0/c/NTg3NjIzNDIwMVpa
https://classroom.google.com/u/0/c/NTg3NTc2MjQ1M1pa
https://classroom.google.com/u/0/c/NTg3NTgxODUwNFpa
YouTube
https://www.youtube.com/watch?v=zLP_X4wyHbY
https://www.youtube.com/watch?v=CDO28Esqmcg&list=PLhwVAYxlh5dvB1MkZrcRZy6x_a2yORNAu
https://www.youtube.com/watch?v=f_2Axf5XAlk&t=3s
publications:
- Yasir Amer Abbas, Razali Jidin, Norziana Jamil, Muhammad Reza Z'aba, M.E. Rusli, “PRINCE IP-Core on Field Programmable Gate Arrays (FPGA)”, Res. J. Appl. Sci. Eng. Technol. Vol. 10,pp. 914–922, 2015.
- Yasir Amer Abbas, Razali Jidin, Norziana Jamil, and Muhammad Reza Z'aba, M.E. Rusli, “Lightweight PRINCE Algorithm IP Core for Securing GSM Messaging using FPGA”, Research Journal of Information. Vol. 8, pp.17-28, 2016
- Yasir Amer Abbas, Razali Jidin, Norziana Jamil, and Muhammad Reza Z'aba,“Reusable Data-Path Architecture for Encryption-then-Authentication on FPGA”, International Review on Computers and Software (IRECOS), vol. 1, pp. 56-63, 2016
- Haider Ismael Shahadi, Razali Jidin, Wing Hung Way, and Yasir Amer Abbas, “Efficient FPGA Architectures for Dual Mode Integer Haar Lifting Wavelet Transform Core”, Journal of Applied Sciences, vol. 14, pp. 436-444, 2014.
Conference
- Yasir Amer Abbas, and Razali Jidin, “Reconfigurable Design of Heterogonous Multiprocessors using FPGA Platforms: A Review,” in UNITEN Student Conference On Research And Development (SCOReD 2012), 2012, pp. 28-31.
- Yasir Amer Abbas, Razali Jidin, and Pooria Varahram,“Evaluation of Reconfigurable Technique for Heterogeneous Multi-core Processors with FPGA Platform,” Image Processing, Image Analysis and Real-Time Imaging (IPIARTI) Symposium 2013, 2013, pp. 18.
- Yasir Amer Abbas, Razali Jidin, Norziana Jamil, Muhammad Reza Z'aba, M.E. Rusli, B. Tariq, Implementation of PRINCE algorithm in FPGA, in: Proc. 6th Int. Conf. Inf. Technol. Multimed., IEEE, 2014: pp. 1–4. doi:10.1109/ICIMU.2014.7066593.
- Yasir Amer Abbas, Razali Jidin, Norziana Jamil, and Muhammad Reza Z'aba,“Securing electrical substation's wireless messaging with a Lightweight Crypto-Algorithm IP core”, IEEE International Conference on Power and Energy (PECon) 2014 , Dec. 2014 , pp. 159-163. (Best Paper Award).
- Saad Al-Azawi, Yasir Amer Abbas, Razali Jidin “Low complexity multidimensional CDF 5/3 DWT architecture”, 9th International Symposium on Communication Systems, Networks & Digital Signal Processing (CSNDSP) 2014 , July 2014, pp. 804-808.